Please enter the search related information in the fields below. Partial information works, e.g. "SP-21" in the "tdoc" field lists all TSG SA documents from 2021. Regular expressions mostly work in all fields (e.g. "2[34].501" in the "Spec" field lists all documents related to 23.501 and 24.501. Capitalization is disregarded, i.e. "3GPP" gives the same results as "3gpp".
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| tdoc | Title | Type / Revs | Source | Spec / CR | S/WID | Release | Meeting | Status | Links |
|---|---|---|---|---|---|---|---|---|---|
| R4-2014242 | UE demodulation requirements with higher BLER | discussion | Apple | NR_L1enh_URLLC-Perf | Rel-16 |
R4-97-e AI: 7.8.1.2.1 |
noted | [WTS] [JSN] | |
| R4-2014243 | CR on requirements with slot aggreagation in FR2 |
CR revised to R4-2017514 |
Apple | 38.101-4 16.2.0 CR#85 catB | NR_L1enh_URLLC-Perf | Rel-16 |
R4-97-e AI: 7.8.1.2.1 |
revised | [WTS] [JSN] |
| R4-2014544 | Discussion on UE demodulation requirements for URLLC | discussion | Intel Corporation | NR_L1enh_URLLC-Perf | Rel-16 |
R4-97-e AI: 7.8.1.2.1 |
noted | [WTS] [JSN] | |
| R4-2015129 | Discussion on eMBB UE performance requirement with pre-emption | discussion | MediaTek inc. | NR_L1enh_URLLC-Perf | Rel-16 |
R4-97-e AI: 7.8.1.2.1 |
noted | [WTS] [JSN] | |
| R4-2015616 | Simulation results on UE PDSCH demodulation reuqirements with higher BLER and low latency | other | Huawei, HiSilicon | NR_L1enh_URLLC-Perf |
R4-97-e AI: 7.8.1.2.1 |
noted | [WTS] [JSN] | ||
| R4-2015617 | Discussion on URLLC UE demodulation requirements with higher BLER and low latency | discussion | Huawei, HiSilicon | NR_L1enh_URLLC-Perf |
R4-97-e AI: 7.8.1.2.1 |
noted | [WTS] [JSN] | ||
| R4-2015620 | CR to TS 38.101-4: Addition of UE performance requirements for FR1 URLLC PDSCH repetitions over multiple slots |
CR revised to R4-2017511 |
Huawei, HiSilicon | 38.101-4 16.2.0 CR#100 catB | NR_L1enh_URLLC-Perf | Rel-16 |
R4-97-e AI: 7.8.1.2.1 |
revised | [WTS] [JSN] |
| R4-2015628 | Summary of simulation results for UE URLLC demodulation performance requirements | other | Huawei, HiSilicon | NR_L1enh_URLLC-Perf |
R4-97-e AI: 7.8.1.2.1 |
noted | [WTS] [JSN] | ||
| R4-2016005 | CR on FRC for UE Higher BLER requirements |
CR revised to R4-2017512 |
Intel Corporation | 38.101-4 16.2.0 CR#110 catB | NR_L1enh_URLLC-Perf | Rel-16 |
R4-97-e AI: 7.8.1.2.1 |
revised | [WTS] [JSN] |
| R4-2016103 | Discussion on UE URLLC demodulation performance requirements with higher BLER | discussion | Ericsson | NR_L1enh_URLLC-Perf | Rel-16 |
R4-97-e AI: 7.8.1.2.1 |
noted | [WTS] [JSN] | |
| R4-2016104 | Simulation results on UE URLLC demodulation performance requirements with higher BLER | other | Ericsson | NR_L1enh_URLLC-Perf | Rel-16 |
R4-97-e AI: 7.8.1.2.1 |
noted | [WTS] [JSN] | |
| R4-2016106 | CR to TS 38.101-4: Performance requirements for URLLC High BLER feature tests |
CR revised to R4-2017513 |
Ericsson | 38.101-4 16.2.0 CR#111 catB | NR_L1enh_URLLC-Perf | Rel-16 |
R4-97-e AI: 7.8.1.2.1 |
revised | [WTS] [JSN] |
| R4-2016462 | Views on URLLC High BLER Demodulation Test Cases | discussion | Qualcomm Incorporated |
R4-97-e AI: 7.8.1.2.1 |
noted | [WTS] [JSN] | |||
| R4-2016504 | CR on FR1 PDSCH Mapping Type B and Processing Capability 2 Requirements |
CR revised to R4-2017516 |
Qualcomm Incorporated | 38.101-4 16.2.0 CR#121 catB | NR_L1enh_URLLC-Perf | Rel-16 |
R4-97-e AI: 7.8.1.2.1 |
revised | [WTS] [JSN] |
| R4-2017511 | CR to TS 38.101-4: Addition of UE performance requirements for FR1 URLLC PDSCH repetitions over multiple slots |
CR revision of R4-2015620 |
Huawei, HiSilicon | 38.101-4 16.2.0 CR#1001 catB | NR_L1enh_URLLC-Perf | Rel-16 |
R4-97-e AI: 7.8.1.2.1 |
agreed | [WTS] [JSN] |
| R4-2017512 | CR on FRC for UE Higher BLER requirements |
CR revision of R4-2016005 |
Intel Corporation | 38.101-4 16.2.0 CR#1101 catB | NR_L1enh_URLLC-Perf | Rel-16 |
R4-97-e AI: 7.8.1.2.1 |
agreed | [WTS] [JSN] |
| R4-2017513 | CR to TS 38.101-4: Performance requirements for URLLC High BLER feature tests |
CR revision of R4-2016106 |
Ericsson | 38.101-4 16.2.0 CR#1111 catB | NR_L1enh_URLLC-Perf | Rel-16 |
R4-97-e AI: 7.8.1.2.1 |
agreed | [WTS] [JSN] |
| R4-2017514 | CR on requirements with slot aggregation in FR2 |
CR revision of R4-2014243 |
Apple | 38.101-4 16.2.0 CR#851 catB | NR_L1enh_URLLC-Perf | Rel-16 |
R4-97-e AI: 7.8.1.2.1 |
agreed | [WTS] [JSN] |
| R4-2017516 | CR on FR1 PDSCH Mapping Type B and Processing Capability 2 Requirements |
CR revision of R4-2016504 revised to R4-2017665 |
Qualcomm Incorporated | 38.101-4 16.2.0 CR#1211 catB | NR_L1enh_URLLC-Perf | Rel-16 |
R4-97-e AI: 7.8.1.2.1 |
revised | [WTS] [JSN] |
| R4-2017665 | CR on FR1 PDSCH Mapping Type B and Processing Capability 2 Requirements |
CR revision of R4-2017516 |
Qualcomm Incorporated | 38.101-4 16.2.0 CR#1212 catB | NR_L1enh_URLLC-Perf | Rel-16 |
R4-97-e AI: 7.8.1.2.1 |
agreed | [WTS] [JSN] |
20 documents (0.34116291999817 seconds)