[{"name":"R1-1904266","title":"Scheduling of multiple DL\/UL TBs for eMTC","source":"Intel Corporation","contact":"Seunghee Han","contact-id":47329,"tdoctype":"other","for":"Discussion","abstract":"","secretary_remarks":"","agenda_item_sort_order":15,"ainumber":"6.2.1.3","ainame":"Scheduling of multiple DL\/UL transport blocks","tdoc_agenda_sort_order":42660,"status":"not treated","reservation_date":"2019-03-27 18:44:40","uploaded":"2019-03-30 07:20:39","revisionof":"","revisedto":"","release":"Rel-16","crspec":"","crspecversion":"","workitem":[{"winame":"LTE_eMTC5-Core"}],"crnumber":"","crrevision":"","crcategory":"","tsg_crp":"","lsreplyto":"","lsto":"","Cc":"","lsoriginalls":"","lsreply":"","link":"https:\/\/www.3gpp.org\/ftp\/TSG_RAN\/WG1_RL1\/TSGR1_96b\/Docs\/R1-1904266.zip","group":"R1","meeting":"R1-96","year":2019,"uicc_affected":null,"me_affected":null,"ran_affected":null,"cn_affected":null,"clauses_affected":null,"crsinpack":null,"crsinpacknumber":0}]