[{"name":"R1-162588","title":"DCI design for short TTI","source":"Huawei, HiSilicon","contact":"Brian Classon","contact-id":45750,"tdoctype":"other","for":"","abstract":"","secretary_remarks":"","agenda_item_sort_order":112,"ainumber":"7.3.10.2","ainame":"Channel design for shortened TTI","tdoc_agenda_sort_order":0,"status":"available","reservation_date":"2016-03-31 01:06:19","uploaded":"2016-04-01 23:09:33","revisionof":"","revisedto":"","release":"","crspec":"","crspecversion":"","workitem":"","crnumber":"","crrevision":"","crcategory":"","tsg_crp":"","lsreplyto":"","lsto":"","Cc":"","lsoriginalls":"","lsreply":"","link":"https:\/\/www.3gpp.org\/ftp\/TSG_RAN\/WG1_RL1\/TSGR1_84b\/Docs\/R1-162588.zip","group":"R1","meeting":"R1-84","year":2016,"uicc_affected":null,"me_affected":null,"ran_affected":null,"cn_affected":null,"clauses_affected":null,"crsinpack":null,"crsinpacknumber":0}]